package XunChunCPU.common.Bundles

import XunChunCPU.common.CommonConfig._ 
import chisel3._
import XunChunCPU.common.ReadyValid

class ExeInfo 
    extends Bundle{
    val OperA = Output(UInt(regLen.W))
    val OperB = Output(UInt(regLen.W))
    val regwe = Output(Bool())
    val wAddr = Output(UInt(regAddrLen.W))
    val op = Output(UInt(8.W))
    val AFromReg = Output(Bool())
    val BFromReg = Output(Bool())
    val ARegAddr = Output(UInt(5.W))
    val BRegAddr = Output(UInt(5.W))
}